Patent Document 1 (JP-2011-71441A) discloses a stacked wafer structure which includes semiconductor wafers each including a plurality of semiconductor chips and stacked one on another. The stacked semiconductor wafers are connected to each other via bumps and silicon through-vias provided in the respective semiconductor wafers. The stacked wafer structure is cut along predetermined dicing lines defined between the semiconductor chips to be thereby divided into the individual semiconductor chips.